1. Field of the Invention
The present invention relates to a testing system; in particular, the present invention relates to a testing system for testing semiconductor package stacking chips.
2. Description of Related Art
Currently available portable electronic products like smartphones, mobile computing products and various electronic consumer devices all seek higher semiconductor functionalities and performance under the conditions of limited occupation areas and least thickness and weight with the lowest fabrication costs, so certain manufacturers have recognized such trends and devoted efforts specifically on the integration of semiconductor chips, and also developed the formation of stacked multiple package integration by means of chip stacking or die stacking package.
Such a stacked multi-package integration can be generally categorized into two types, respectively referred as package-on-package (PoP) and package-in-package (PiP). More specifically, in terms of the integral structure of PoP, at present, the technology utilized in industry can lay out more than one hundred contacts on a single chip of square centimeter area, which typically comprises a two-layer structure consisting of a first package (top package) and a second package (bottom package), wherein the first package (top package) is stacked on top of the second package (bottom package), with each package surface including more than one hundred micro contacts (solder balls) for solder connection, and the contacts respectively on the first package and the second package are mutually connected by means of precision soldering technologies. So far, the chip-under-test fabricated in this way is still individually inspected all through visual and manual test operations.
In the stack chip package, upon stack integrating the top chip with the bottom chip, it is necessary to perform test processes on final test yield. Therefore, in a conventional stack chip package, it is required to manually place an individual top chip onto an individual bottom chip in stack so as to perform the final test. However, in case that low yields or continuous errors do occur from the test results, it may become difficult to clearly differentiate whether the top chip or the bottom one causes such problems. Seeking other approaches for solution may complicate the entire process, if unable to efficiently identify the problem source.
Consequently, it is desirable to provide a technical solution which enables the use of a correct, error-free top chip as a testing chip, conjunctively with the automatic pick-up and placement as well as categorization for the under-test bottom chip, and electrically connects the testing chip to the under-test bottom chip to perform the test operation; hence, it is possible to automatically categorize the bottom chip before the process of stack chip package thereby more significantly increasing the final test efficiency and also saving manpower costs, thus offering an optimal solution.